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ADV7195
PROGRAMMABLE ADAPTIVE FILTER CONTROL
If the Adaptive Filter Mode is enabled (Progressive Scan Mode
only), it is possible to compensate for large edge transitions on
the incoming Y data. Sensitivity and attenuation are all pro-
grammable over the I 2 C. For further information refer to
Sharpness Filter Control and Adaptive Filter Control section.
INPUT/OUTPUT CONFIGURATION
Table I shows possible input/output configurations when using
the ADV7195.
Table I.
10
0
– 10
– 20
– 30
– 40
– 50
– 60
10
0
– 10
– 20
– 30
– 40
– 50
Input Format
YCrCb Progressive Scan
4:2:2
4:4:4
YCrCb HDTV
4:2:2
4:4:4
RGB Progressive Scan
4:4:4
RGB HDTV
4:4:4
Async Timing Mode
All Inputs
Output
2 ×
1 × or 2 ×
1 ×
1 ×
2 ×
1 ×
1 ×
– 70
– 80
0 5 10 15 20 25 30
Figure 10. Interpolation Filter–CrCb Channels/Cr 4:4:4
Input Data
MPU PORT DESCRIPTION
The ADV7195 support a 2-wire serial (I 2 C-compatible) micro-
processor bus driving multiple peripherals. Two inputs, Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7195 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 11. The
LSB sets either a read or write operation. Logic Level “1” corre-
sponds to a read operation while Logic Level “0” corresponds to
a write operation. A1 is set by setting the ALSB pin of the
ADV7195 to Logic Level “0” or Logic Level “1.” When ALSB is
set to “0,” there is greater input bandwidth on the I 2 C lines,
which allows high-speed data transfers on this bus. When ALSB
is set to “1,” there is reduced input bandwidth on the I 2 C
lines, which means that pulses of less than 50 ns will not pass
into the I 2 C internal controller. This mode is recommended
for noisy systems.
– 60
1
1
0
1
0
1
A1
X
– 70
ADDRESS
– 80
0
5
10
15
20
25
30
CONTROL
SETUP BY
ALSB
Figure 8. 2 × Interpolation Filter 4-Channel
READ/ WRITE
CONTROL
0 WRITE
1 READ
10
Figure 11. Slave Address
0
To control the various devices on the bus the following protocol
– 10
– 20
– 30
– 40
– 50
– 60
– 70
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/ W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
– 80
0
5
10
15
20
25
30
condition is where the device monitors the SDA and SCL lines
waiting for the Start condition and the correct transmitted
Figure 9. Interpolation Filter–CrCb Channels/Cr 4:2:2
Input Data
REV. A
address. The R/ W bit determines the direction of the data.
–11 –
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